Ilia Saber

Engineering Portfolio
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About me

Hey, I’m Ilia Saber, an Electrical Engineering and Artificial Intelligence Systems Engineering student at Western University. I get to learn both sides of modern technology: how electronic hardware is designed and built, and how to bring software and AI to life on top of it.

  • University Western University
  • Education Electrical Engineering & Artificial Intelligence Systems Engineering
CHIP DESIGN & DIGITAL LOGIC

Chip Design

I am passionate about digital logic, VLSI, and integrated circuit design. My focus spans designing discrete logic gates, combining MOS transistors to build functional IC blocks, writing HDL in Verilog and SystemVerilog, implementing flows on FPGAs, and verifying clock domain crossing logic for reliable high-speed operation.

ELECTRONICS & EMBEDDED SYSTEMS

Electronics & Embedded

I like designing custom PCBs, programming microcontrollers, and bringing up hardware from bare boards to fully operational systems. I am particularly drawn to the high-speed side—analyzing signal integrity, debugging with oscilloscopes and VNAs, and understanding physical behavior.

SOFTWARE & APPLIED AI

Software & AI

I enjoy writing software for APIs, automating workflows, and deploying applied machine learning to solve problems—ranging from classification models and time-series forecasting to designing neural networks for image processing.

Flight Tracker

Live Aircraft Telemetry & Display

An embedded hardware project driven by an ESP32 microcontroller paired with an E-Paper display. The system queries aviation APIs to fetch live telemetry for aircraft within a custom geographic Bounding Box (BBox).

Every 1.5 minutes, the system parses data and renders key details: aircraft callsign, aircraft type, altitude, ground speed, heading/direction, and airline logo.

Includes a custom PCB design for streamlined power management and compact hardware connectivity.

ESP32 E-Paper Display REST APIs PCB Design C++
Flight Tracker PCB Schematic

Async FIFO (FPGA)

Clock Domain Crossing (CDC) Simulation

A dual-clock asynchronous FIFO designed in SystemVerilog to enable reliable data transfers between asynchronous clock domains without setup/hold timing violations or metastability.

Utilizes multi-stage synchronizers with Gray code pointer conversions to reliably pass read and write addresses across domains, alongside accurate Full and Empty status flag generation logic.

SystemVerilog CDC Synchronizers Libero SoC ModelSim
Asynchronous FIFO Simulation Waveform

Capstone Project

In Progress (ECE 4416 Capstone)

FPGA-Based BLDC/PMSM Motor Controller Using Field-Oriented Control (FOC)

Designing and building a deterministic hardware controller on an FPGA for three-phase Brushless DC (BLDC) and Permanent Magnet Synchronous Motors (PMSM) using Field-Oriented Control (FOC) algorithms.

Implemented direct hardware modules for Clarke & Park coordinate transformations, Proportional-Integral (PI) current loop regulation, inverse transformations, Space Vector PWM (SVPWM) generation, and rotor position sensing interfaces to execute real-time closed-loop motor control with high efficiency.

FPGA Field-Oriented Control (FOC) SVPWM BLDC / PMSM Motors SystemVerilog

Experience

StarTech.com

Product Development / Verification Specialist Intern

May – August 2025

May – August 2026

  • Tested and validated high-speed cable hardware (Ethernet, HDMI, DisplayPort, USB) through electrical compliance, signal-integrity, and mechanical testing using oscilloscopes and VNAs, resulting in verified compliance with industry standards and reliable high-speed performance.
  • Performed electrical compliance testing to validate power delivery, data integrity, and mechanical durability on peripheral connectivity devices (USB hubs and docking stations) using oscilloscopes and multimeters, documenting results to StarTech.com standards.
  • Collaborated with engineering, supply chain, and operations teams to adapt testing strategies for supplier transitions, enabling efficient hardware re-qualification while maintaining compliance and delivery timelines.
  • Documented engineering data in detailed reports, ensuring traceability, knowledge transfer, and data-driven design improvements while demonstrating strong written documentation skills.
  • Performed time-domain signal analysis using oscilloscopes (eye diagrams, jitter, duty cycle, rise/fall), identifying signal-quality margins and potential integrity issues at high data rates.
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